Field of the Invention
The present invention relates to an integrated circuit, and in particular to a bottommost layered-level metal routing design for an integrated circuit.
Description of the Related Art
For an integrated circuit design, a shrinkage channel length for an electronic device and an increased amount of input/output connections (pin account) for multi-functional cells are required. Accordingly, the fin-like electronic devices for the increase pin accesses for the cells have been developed. For a conventional integrated circuit, however, the density of routings for input/output connections of fin-like electronic devices is limited due to design-rule restrictions for the bottommost layered-level metal (also referred to as first-level metal (M1)) routings.
Thus, a novel integrated circuit and a routing design of the integrated circuit are needed.